FReLU bias=False bug fix (#1607)

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Glenn Jocher 2020-12-10 13:07:10 -08:00 committed by GitHub
parent 61fb2dbd20
commit 883a5aff5a
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@ -65,7 +65,7 @@ class MemoryEfficientMish(nn.Module):
class FReLU(nn.Module):
def __init__(self, c1, k=3): # ch_in, kernel
super().__init__()
self.conv = nn.Conv2d(c1, c1, k, 1, 1, groups=c1)
self.conv = nn.Conv2d(c1, c1, k, 1, 1, groups=c1, bias=False)
self.bn = nn.BatchNorm2d(c1)
def forward(self, x):